Friday, 9 October 2015

IBM Breakthrough Improves Carbon Nanotube Scaling Below 10nm


IBM – Beneficial Scaling Abilities in Carbon Nanotubes

IBM has invested a great amount of time and effort in researching carbon nanotubes – CNTs in the past few years. The presence of single walled carbon nanotubes together with their marvellous semiconductor properties happened independently at NEC as well as at IBM with Big Blue being interested in capitalizing on the discovery for over a decade.

Researchers at IBM published a paper wherein they claimed to have demonstrated extremely beneficial scaling abilities in carbon nanotubes. Discussions were on, regarding the difficulties of scaling semiconductors since the distance between features tends to contract with each passing generation.

However the specific breakthrough which IBM tends to claim is in an area of chip design and not much has been discussed over it. In the case of conventional silicon, a known problem as semiconductors tends to shrink and the contact area from the metal and semiconductor has not been scaling.

Smaller contact area, generally lead to increased resistance which means higher heat. Manufacturers have battled against these developments with various methods. However the lack of contact scaling seems to be one of the main barriers in pushing silicon to ever smaller sizes.

Carbon Nanotube Technology – Solution to Problem

IBM is of the opinion that its carbon nanotube technology could solve that issue. EETimes has an amazing write-up of the technology, though it amusingly refers to EUV lithography as `already in place’, a declaration which would surprise Intel as well as TSMC. With the recent innovation,Shu-Jen Han, IBM Manager of nanoscale science and technology at its T.K. Watson Research Centre informed EE Times that `they know how to scale and it is no longer the limiting factor for carbon nanotube transistors.

 The new contacts are measured in angstroms and they have just 36 k-ohms of resistance inclusive of both ends’. The new method involves welding – nanowelding – nanotube with molybdenum prior to self-align as transistor channels. The last step is to heat the assembly to around 850C, melting the molybdenum off and developing carbide. Richard Doherty of Envision engineering is of the opinion that this solution gives IBM an exceptional advantage in scaling along the way to 1.8nm.

Group Evaluating Changes to Measuring Standards

IBM could be preparing the technology, in readiness at the 5nm node for the introduction at 3nm and below, according to EETimes. With the method which has already been proven in theory at 9nm, it seems to be a bit of a block to further scaling. However, there are some cautions pointed to these findings.

Firstly, the fact that IBM is presently capable of building p-type transistors utilising this method which does not mean that the technology seems useless. Several of the proposed near term solutions for enhanced silicon scaling depends on various materials for the p-channel and n-channel, though it positively presents additional complexity.

The International Technical Roadmap for Semiconductors had not been issued since 2013 and the group is presently evaluating changes to its measuring standards for formulating latest reports. However the 2013 data set is yet online and viewing it, the roadmap for near term introduction of carbon nanotubes is not very appealing.

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