Wednesday, 19 February 2014

Intel launches 15-core Xeon E7 v2 with three ring buses

15-core Xeon E7 v2
As a series of E7 -4000 Intel offers its new server processors. However, the Xeons are based on the Ivy Bridge architecture and were upgraded primarily by new bus systems and AVX. They are previously codenamed Ivy Bridge -EX processors, Intel now on the series E7 -4000. The entire platform was previously codenamed Ivytown. Commonly is also the name E7 - v2, because these processors are the successor of the 2011 series introduced E7.

As this is also E7 - v2 designed for servers with up to eight sockets in which as many full x86 cores are working in parallel. Even if the model number 4000 suggests a proximity to the Core i 4000 Haswell, the Xeons are always based on the previous desktop architecture. In the case of E7 - v2 is the Ivy Bridge, Intel's first design with 22 nm feature size. By now probably good routine production process had started, the power consumption could remain largely the same and the fastest models are coming with up to 155 watts TDP.

The E- 8880 v2 is also of 15- Kernel, which only needs 130 watts. While Haswell processors are manufactured with various these, Intel has chosen for the Xeon E7 - v2 for only one reason. That is, It can offer three blocks for the L3 cache, each of which is connected to three units with up to five cores. Therefore, there is a flexible option for the number of nuclei is possible. In a study submitted to the Conference ISSCC Intel speaks of "chop options" presentation in their presentation. So they gave the reason for the right block with five cores and L3 cache should not actually be present in up to ten cores. So Intel just needs the manufacture for all new Xeons and can configure the functional cores so that the desired number of cores needed.

Since there is not a shared L3 cache for all cores as with previous Intel designs, the cores cannot communicate over a single ring bus. Which allow a direct connection of the three 5 -core blocks. Because of the location in the middle of this L3 cache can communicate with the left directly with adjacent data. The three ring buses are two Home Agents controlled with two memory controllers while since Sandy Bridge was always only one such controller for bus and memory interface at the desktop and mobile CPUs. Overall, the cache can be large with a fully equipped E7 v2 up to 37.5 Mbytes; an entire new Xeon consists of up to 4.3 billion transistors.

Production costs are also reflected in their price. In the cores themselves, there are the Ivy Bridge design extensions to the instruction sets. Thus, the E7 - v2 now dominated by AVX vector processing, as a new interface, there are PCI Express 3.0 with 32 lanes per socket. That does not sound much, but is also extended by the revised QPI bus, which connects the base. The new QPI 1.1 depending on the model with up to eight GT / s at work.

 In addition, there are now eight per socket instead of four memory channels. The two of them can also be connected together, which effectively corresponds to DDR3 - 2666. As individual channels memory is possible by DDR3 -1600. Both modes are supported by the storage drivers, codenamed Jordan Creek, which have not changed over the older Xeons. Using these blocks can be addressed up to 12 DIMMs per channel, giving a maximum of 48 terabytes of RAM for an eight- socket system with the still rare 64 -gigabyte Registered DIMMs.

The processor can be operated in lockstep mode with enhanced error correction but the faster performance mode with channel bundling is more than in half the RAM. It comes in the configuration of a system with the new Xeons so on the application range in some applications benefit from a lot of memory, other scale better with more cores or cache. Therefore, there is a need for the E7 - v2 in so many varieties, 20 models to choose from.

Because so different application profiles and processors, Intel also specifies different values for the benefit of computing power compared to the previous generation. At least twice as fast -with only 50 % more cores used in the server when as databases or Web applications are running. In highly optimized code with AVX for supercomputers gives a better result of three and a half times up to speed.

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